Bounded Property Checking with Symbolic Simulation

Steadily increasing design sizes, make the verification a bottleneck in modern design flows of digital hardware and embedded software systems. Up to 75% of the overall design costs are due to the verification task. Formal methods have been proposed to accompany commonly used simulation approaches. In this paper we combine property checking and symbolic simulation to make these techniques applicable to larger designs and to seamlessly integrate formal verification and standard simulation. Our experimental results show a run time gain over standard symbolic model checking and SATbased bounded model checking for certain classes of circuits and properties.